Semiconductor device

ABSTRACT

A T-CAM array is provided made up of ternary dynamic CAM cells each including a plurality of transistors. A refresh operation can be performed while reading out stored data to a match line using the same current path as that for a search operation, thereby providing a highly integrated array without reducing the original search speed. A rewrite data line is provided in parallel with a match line, and rewrite transistors are inserted between the rewrite data line and the storage nodes within each dynamic CAM cell. With this cell configuration, the data stored at each storage node is read out to the match line one at a time and rewritten through the rewrite data line to carry out a refresh operation.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a Continuation application of U.S. application Ser.No. 10/755,333 filed Jan. 13, 2004. Priority is claimed based on U.S.application Ser. No. 10/755,333 filed Jan. 13, 2004, which claims thepriority date of Japanese Patent Application No. 2003-150246 filed May28, 2003, all of which is incorporated by reference.

BACKGROUND OF THE INVENTION Field of the Invention

The present invention relates to a semiconductor device, and moreparticularly to a semiconductor device including content addressablememory cells (CAM cells) which compare data stored at their storagenodes with entered data. The present invention even more particularlyrelates to a semiconductor device including a highly integratedhigh-speed T-DCAM array made up of ternary dynamic CAM cells (T-DCAMcells) which store ternary data while refreshing it.

Description of the Related Art

The explosive growth of the Internet has increased the size of thetables required for network routers and switches, making it necessary toincrease the table search speed. Conventionally, the calculationalgorithm has been improved to speed up the table search. Such a methodfor enhancing the processing power, however, is approaching its limit.Furthermore, there is the problem of software solutions lacking inflexibility for supporting various network standards. Accordingly, theternary content addressable memory (T-CAM) is attracting attention as ahardware solution for solving these problems.

A T-DCAM cell configuration of a ternary dynamic content addressablememory (T-DCAM) is described in Records of the 2000 IEEE InternationalWorkshop on Memory Technology, Design and Testing, pp. 101-105, 2000.FIG. 2 is a diagram of this cell configuration taken from FIG. 2 of theabove document. This cell has storage nodes N1 and N2 made up of NMOStransistors T1, T2, T4, and T6 and capacitors C1 and C2 and storesternary data.

The cell has an XNOR operation function implemented by the NMOStransistors T3, T4, T5, and T6 to compare its stored data with entereddata.

First of all, its memory function will be described.

The ternary data uses three distinct values: data 1, data 0, and data X,which indicates the so-called DON'T CARE state. Assuming that a highvoltage level represents a logic “1” and a low voltage level representsa logic “0”, the combination of the logic values of the storage nodes N1and N2 corresponding to data 1 is “1” and “0” expressed as (1, 0); thatcorresponding to data 0 is “0” and “1”, or (0, 1); and thatcorresponding to data X is “0” and “0”, or (0, 0). The stored data isrefreshed through the transistors T1 and T2, and read out and rewrittenby use of sense amplifiers (not shown in the figure) connected to bitlines BL1 and BL2.

The XNOR operation function will be described below. The data to becompared with the stored data is ternary data and is entered throughsearch lines SL1 and SL2. This ternary data uses three values: data 1,data 0, and data MASK, which indicates the so-called MASK state. In thecomparison operation, if the entered data coincides with the storeddata, since no current path is formed between a match line ML currentlyprecharged at a high voltage and a discharge line DCL set at a lowvoltage (for example, ground potential VSS), the match line remains atthe precharge voltage (the high voltage). If, on the other hand, they donot coincide, the match line is discharged since a current path isformed between the match line ML and the discharge line DCL.

A match line sense amplifier (not shown) senses changes in the voltageof the match line in the above operation to produce a comparison result.It should be noted that if the stored data is data X, or the entereddata is data MASK, it is determined that the entered data coincides withthe stored data since no current path is formed between the match lineML and the discharge line DCL.

Another T-DCAM cell configuration is described in Japanese Laid-OpenPatent Publication 2002-197872. FIG. 3 is a diagram of this cellconfiguration taken from FIG. 2 of the above patent publication. Thiscell has an XNOR operation function implemented by the transistors T3,T4, T5, and T6, as does the cell described in Records of the 2000 IEEEInternational Workshop on Memory Technology, but the componentconfigurations for their memory functions are different. Specifically,two NMOS transistors T9 and T10 are newly added to the configurationshown in FIG. 2. The cell shown in FIG. 3 having such a configurationstores ternary data, as does the cell shown in FIG. 2. The rewriteoperation is carried out through the transistors T1 and T2, as in thecell having the configuration shown in FIG. 2. In the refresh operation,however, the present cell performs read operation in a different way,that is, by use of the newly added transistors T9 and T10. Specifically,when the transistors T9 and T10 are activated, signals corresponding tothe conductive states of the transistors T4 and T6 determined by thestored data are generated on the bit lines BL1 and BL2.

Prior to the filing of this application, the present inventors studiedhow to increase the speed and the integration density of the T-CAM arrayand found that, of all prior art T-DCAM cells having a small cell area,the type of cell shown in FIG. 3 is important since it has the followingtwo advantages.

One is that theoretically this cell can operate without capacitors,eliminating (or alleviating) the need for forming capacitors, which isan obstacle to miniaturization.

The other is that if this cell is formed of only NMOS transistorswithout using capacitors, the number of masks to be employed is reduced,which is expected to lead to reduced cost per bit.

The present inventors, however, have found that this cell has thefollowing three problems.

The first problem is its reduced XNOR operation speed. As describedabove, the cell configuration shown in FIG. 3 is obtained by adding thetransistors T9 and T10 to the configuration shown in FIG. 2. Such aconfiguration might increase the diffusion capacitances at intermediatenodes M1 and M1, delaying the output signal to the match line ML.Increased XNOR operation time is detrimental to speeding-up of theoperation of the T-CAM array.

The second problem is the increased sense amplifier area. As describedabove, a T-DCAM array using the cell shown in FIG. 3 must sense(discriminate) not only the signal generated on the match line ML in thesearch operation but also the read signals generated on the bit linesBL1 and BL2 in the refresh operation. Therefore, sense amplifiers mustbe provided for all match lines and bit lines, reducing the celloccupancy ratio, which is detrimental to enhancement of the integrationdensity of the T-CAM array.

The third problem is the deteriorated retention characteristic. Reducingthe size of a transistor increases its leakage current, as is generallyknown. In the cell configuration shown in FIG. 3, an increase in theleakage currents of the transistors T1 and T2 leads to a reduction inthe stored data retention time (or simply the retention time), requiringfrequent refresh operation, which results in increased refresh powerconsumption of the T-CAM array.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a T-DCAM cellconfiguration for a highly integrated high-speed T-CAM array.

A typical arrangement of the present invention will be described asfollows.

A rewrite data line RWD is provided in parallel with the match line ML,and transistors for rewrite operation are inserted between the rewritedata line and the storage nodes within the T-DCAM cell. The refreshoperation includes the steps of: sequentially reading the data stored ateach storage node and outputting it to the match line; discriminating(detecting) the read data by use of the sense amplifier connected to thematch line; transferring the read data to the rewrite data line;, andwriting (rewriting) the data to the storage nodes through the rewritetransistors.

With this arrangement, the search operation and the read operation arecarried out using the same current path formed between the match lineand the grounded electrode, making it possible to perform refreshoperation while maintaining the high speed of the search operation.Furthermore, since sense amplifiers are provided for only the matchlines, the T-CAM array area can be reduced.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a diagram showing a configuration example of a ternary dynamicCAM cell made up of 8 transistors according to the present invention.

FIG. 2 is a diagram showing a configuration example of a prior artternary dynamic CAM cell made up of 6 transistors and 2 capacitors.

FIG. 3 is a diagram showing a configuration example of a prior artternary dynamic CAM cell made up of 8 transistors and 2 capacitors.

FIG. 4 is a diagram showing a configuration example of a ternary CAMarray made up of ternary dynamic CAM cells such as that shown in FIG. 1.

FIG. 5 is a diagram showing the write operation timing of the ternarydynamic CAM cell shown in FIG. 1.

FIG. 6 is a diagram showing the search operation timing of the ternarydynamic CAM cell shown in FIG. 1.

FIG. 7 is a diagram showing truth values for the search operation of theternary dynamic CAM cell shown in FIG. 1.

FIG. 8 is a diagram showing the refresh operation timing of the ternaryCAM array shown in FIG. 4.

FIG. 9 is a diagram showing the read operation timing of the ternary CAMarray shown in FIG. 4.

FIG. 10 is a block diagram showing a configuration example of a ternaryCAM using the ternary dynamic CAM cell shown in FIG. 1.

FIG. 11 is a diagram showing a first portion of a layout example of aternary dynamic CAM cell using planar transistors.

FIG. 12 is a diagram showing a second portion of the layout example ofthe ternary dynamic CAM cell using the planar transistors.

FIG. 13 is a diagram showing a third portion of the layout example ofthe ternary dynamic CAM cell using the planar transistors.

FIG. 14 is a diagram showing a fourth portion of the layout example ofthe ternary dynamic CAM cell using the planar transistors.

FIG. 15 is a cross-sectional view of the layout structure in FIG. 14taken along line A-A′.

FIG. 16 is a diagram showing a first portion of a layout example of aternary dynamic CAM cell using vertical transistors.

FIG. 17 is a diagram showing a second portion of the layout example ofthe ternary dynamic CAM cell using the vertical transistors.

FIG. 18 is a diagram showing a third portion of the layout example ofthe ternary dynamic CAM cell using the vertical transistors.

FIG. 19 is a diagram showing a fourth portion of the layout example ofthe ternary dynamic CAM cell using the vertical transistors.

FIG. 20 is a diagram showing a fifth portion of the layout example ofthe ternary dynamic CAM cell using the vertical transistors.

FIG. 21 is a cross-sectional view of the layout structure in FIG. 16taken along line B-B′.

FIG. 22 is a cross-sectional view of the layout structure in FIG. 17taken along line C-C′.

FIG. 23 is a diagram showing another configuration example of a ternarydynamic CAM cell made up of 8 transistors and 2 capacitors.

FIG. 24 is a diagram showing another configuration example of a ternarydynamic CAM cell made up of 8 transistors.

FIG. 25 is a diagram showing still another configuration example of aternary dynamic CAM cell made up of 8 transistors.

FIG. 26 is a diagram showing yet another configuration example of aternary dynamic CAM cell made up of 8 transistors.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Preferred embodiments of the present invention will be described belowwith reference to the accompanying drawings.

Each circuit element constituting each block of the following preferredembodiments is not limited to any particular type. However, typicallythey are formed on, for example, a single monocrystalline siliconsemiconductor substrate by use of a known semiconductor integratedcircuit technique such as a CMOS (complementary MOS transistor)technique.

<First Embodiment>

<<T-DCAM cell configuration example>>

FIG. 1 shows a configuration example of a T-DCAM cell according to afirst embodiment of the present invention. This cell includes 8 NMOStransistors. The transistors and nodes in the figure which correspond tothose in FIG. 2 or 3 are denoted by like numerals to simplify theexplanation. Specifically, these common transistors are the transistorsT1, T2, T3, T4, T5, and T6. The T-DCAM cell configuration of the firstembodiment has the following two characteristics.

One is that the capacitors C1 and C2 employed in the cells shown inFIGS. 2 and 3 are omitted, and the storage nodes N1 and N2 are formed ofparasitic capacitances instead.

The other characteristic is that a rewrite data line RWD is provided inparallel with the match line ML, and rewrite transistors T7 and T8 areinserted between the rewrite data line RWD and the storage nodes N1 andN2. The cell configuration will be described by focusing on theadditional transistors T7 and T8.

The source of the transistor T7 is connected to the gate of thetransistor T4 together with the source of the transistor T1 so that thediffusion capacitance (not shown) and the gate capacitance of thetransistor T4 together form the storage node N1. Likewise, the source ofthe transistor T8 is connected to the gate of the transistor T6 togetherwith the source of the transistor T2 so that the diffusion capacitance(not shown) and the gate capacitance of the transistor T6 together formthe storage node N2. Further, the gate of the transistor T7 is connectedto a rewrite column select line RW2, while the gate of the transistor T8is connected to a rewrite column select line RW1. Still further, thedrains of the transistors T7 and T8 are connected to the rewrite dataline RWD.

With reference to FIG. 4, description will be made below of theconfiguration of a T-CAM array using T-DCAM cells having theconfiguration shown in FIG. 1.

The configuration shown in FIG. 4 includes m*n T-DCAM cells (CL11 toCLmn). A row decoder XDEC selects a word line from among a plurality ofword lines WLj (j=1, 2, . . . , m) according to a plurality of rowaddress signals entered through a row address bus XBS (described later).A compare signal detector CSDTC precharges match lines MLj (j=1, 2, . .. , m) and discriminates (detects) the small signals generated on thematch lines MLj. The compare signal detector CSDTC also generatessignals based on the small signal detection results and outputs them toa hit signal bus HBS (described later) and write data lines RWDj (j=1,2, . . . , m) Specifically, the compare signal detector CSDTC forperforming these operations may be configured such that it includes, foreach match line, a precharge circuit, a sense amplifier, and a rewritedata line drive circuit. A search/bit line controller SBCTL drivessearch lines SLk (k=1, 2, . . . , n) and bit lines BLk (k=1, 2, . . . ,n) according to an entry, a search key, and a column address enteredthrough a data bus DBS, and a plurality of mask signals entered througha mask signal bus MKBS. Further, a rewrite column select circuit RWSdrives a rewrite column select line RW corresponding to the columnaddress entered through the data bus DBS. It should be noted that theterm “entry” here refers data stored in a T-DCAM cell. Entries are inputto cells through bit lines. Further, the term “search key” here refersto data that is compared with an entry. Search keys are input to theT-CAM array through search lines. In this array configuration, each cellhaving the configuration shown in FIG. 1 performs write and searchoperations on ternary data, as does the conventional cell. Furthermore,the T-CAM array activates the search lines one at a time to read storeddata for each column in order to perform refresh operation, as describedlater. For simplicity, it is assumed that the row decoder XDEC, thecompare signal detector CSDTC, the search/bit line controller SBCTL, andthe rewrite column select circuit RWS are directly connected to theconfiguration shown in FIG. 1.

First of all, to read out the data stored at the storage node N1, thesearch line SL2 is activated with the search line SL1 held in anunactivated state such that conduction occurs between the match line MLand the intermediate node M1. At that time, if the transistor T4 is on,a current path is formed between the match line ML and the groundedelectrode. If, on the other hand, the transistor T4 is off, no currentpath is formed between the match line ML and the grounded electrode.That is, whether a current path is formed between the match line ML andthe grounded electrode depends on the data stored in the T-DCAM cell,and a read signal corresponding to the stored data is generated on thematch line ML. Then, the above compare signal detector discriminatesthis signal, generates a signal corresponding to the stored data, andtransfers it to the rewrite data line RWD. Lastly, the rewrite columnselect line RW2 is activated to write (rewrite) the stored data to thestorage node N1 through the rewrite transistor T9.

This completes a refresh operation on the data stored at the storagenode N1. As is easily understood from the above description, the searchline SL1 and the rewrite column select line RW1 are activated to refreshthe data stored at the storage node N2.

With the above basic operations in mind, detailed description will bemade below of the operation of a T-DCAM cell having the configurationshown in FIG. 1.

<<Description of Write Operation>>

In the following description of the operation, reference numeral VSSdenotes the ground potential, and VDD denotes the power supply voltage.Further, reference numeral VPCH denotes the precharge voltage for thematch line, and VPP denotes each boosted dc voltage supplied to the wordline WL and the rewrite control lines RW1 and RW2. It is assumed thatthe precharge voltage VPCH is set higher than the ground potential VSSbut equal to or lower than the power supply voltage VDD. It is furtherassumed that the boosted dc voltage VPP is higher than the power supplyvoltage VDD, and their difference is set larger than the thresholdvalues of the NMOS transistors. The write operation will be describedwith reference to FIG. 5 based on the above assumptions.

In the wait state, the match line ML is precharged to the prechargevoltage VPCH and the other signals (lines) are held at the groundpotential VSS. Then, the bit lines BL1 and BL2 are driven to voltagescorresponding to an input entry. After that, if the word line WL set atthe ground potential VSS has been driven to the boosted dc voltage VPP,the transistors T1 and T2 are turned on. As a result, conduction occursbetween the storage nodes N1 and N2 and their corresponding bit linesBL1 and BL2. FIG. 5 shows a reverse data write operation example. Thesolid lines indicate waveforms illustrating a write operation in whichdata 0, that is, (0, 1), is overwritten with data 1, that is, (1, 0).The broken lines, on the other hand, indicate waveforms illustrating awrite operation in which data 1 is overwritten with data 0. In the caseof the reverse data write operation in which data 0 is overwritten withdata 1, for example, the bit line BL1 set at the ground potential VSS isdriven to the power supply voltage VDD, while the bit line BL2 is heldat the ground potential VSS. Then, when the word line WL has beenactivated, the storage node N1 set at the ground potential VSS is drivento the power supply voltage VDD, and the storage node N2 set at thepower supply voltage VDD is driven to the ground potential VSS. When thevoltages of the storage nodes N1 and N2 have reached voltage levelssubstantially equal to those of their corresponding bit lines BL1 andBL2, the word line WL set at the boosted dc voltage VPP is driven to theground potential VSS, turning off the transistors T1 and T2. Then, thebit lines BL1 and BL2 are driven to the ground potential VSS to returnthe cell to the wait state, thereby completing the write operation.

The above description explains how to write binary data. In an operationto write data X (the third data), the word line WL is activated withboth bit lines BL1 and BL2 held at the ground potential VSS to driveboth storage nodes N1 and N2 to the ground potential VSS. As is easilyunderstood from the above description of the operations, in a T-CAMarray having the configuration shown in FIG. 4, data is written to allT-DCAM cells connected to a selected word line at the same time. Thatis, a write operation is carried out on a row basis, as in the dynamicrandom access memory (DRAM).

<<Description of Search Operation>>

With reference to FIG. 6, description will be made below of the searchoperation of a T-DCAM cell having the configuration shown in FIG. 1. Inthis operation, the transistors T3, T4, T5, and T6 are used to performan XNOR operation to compare a search key and an entry, as in theconventional cell.

First of all, description will be made of search operation on binarydata. In the wait state, the match line ML is precharged to theprecharge voltage VPCH, and the other signals (lines) are held at theground potential VSS. When a search operation begins, the search linesSL1 and SL2 are driven to voltages corresponding to an input search key.In FIG. 6, the solid lines indicate waveforms of the search lines in asearch operation in which the search key is data 1, that is, (1, 0). Thebroken lines, on the other hand, indicate waveforms of the search linesin a search operation in which the search key is data 0, that is, (0,1). The figure also indicates the (voltage) waveforms of the storagenodes when data 1 is stored in the cell. In the case of the searchoperation for data 1, the search line SL1 set at the ground potentialVSS is driven to the power supply voltage VDD with the search line SL2held at the ground potential VSS, turning off the transistor T3 andturning on the transistor T5. As a result, conduction occurs between thematch line ML and the intermediate node M2. At that time, if the T-DCAMcell stores data 1, the transistor T4 is on since the storage node N1 isat a high voltage, and the transistor T6 is off since the storage nodeN2 is at a low voltage.

Accordingly, no current path is formed between the match line ML and thegrounded electrode, and therefore the match line ML is held at theprecharge voltage VPCH. This comparison result is hereinafter referredto as a “hit”. Though not shown in the figure, if, on the other hand,the T-DCAM cell stores data 0, the transistor T4 is off since thestorage node N1 is at a low voltage, and the transistor T6 is on sincethe storage node N2 is at a high voltage. Accordingly, a current path isformed between the match line ML and the grounded electrode through theintermediate node M2, and the match line ML is discharged from theprecharge voltage VPCH toward the grounded potential VSS. Thiscomparison result is hereinafter referred to as a “miss”. The searchoperation for data 0 can be easily understood from the above descriptionof the search operation for data 1. That is, the search line SL2 set atthe ground potential VSS is driven to the power supply voltage VDD withthe search line SL1 held at the ground potential VSS, turning on thetransistor T3 and turning off the transistor T5. As a result, conductionoccurs between the match line ML and the intermediate node M1. At thattime, if the T-DCAM cell stores data 1, as shown in the figure, thetransistor T4 is on since the storage node N1 is at a high voltage, andthe transistor T6 is off since the storage node N2 is at a low voltage.

Accordingly, a current path is formed between the match line ML and thegrounded electrode through the intermediate node M1, and therefore thematch line ML is discharged. That is, the comparison result is a miss.Though not shown in the figure, if, on the other hand, the T-DCAM cellstores data 0, the transistor T4 is off since the storage node N1 is ata low voltage, and the transistor T6 is on since the storage node N2 isat a high voltage. Accordingly, no current path is formed between thematch line ML and the grounded electrode, and therefore the match lineML is held at the precharge voltage VPCH. That is, the comparison resultis a hit.

When the comparison result is a miss, the search line set at the powersupply voltage VDD is driven to the ground potential VSS to turn off thetransistors T3 and T5 when the difference between the precharge voltageand the voltage of the match line, which is currently being discharged,has become sufficiently large. This stops the discharge of the matchline ML. In the figure, reference numeral VSIG denotes a small voltagedifference at which the search line is unactivated. This voltagedifference is hereinafter referred to as a compare signal. The value(voltage level) of the compare signal VSIG is small enough for the abovecompare signal detector to properly discriminate it from the prechargevoltage of the match line ML. Lastly, according to the determination(discrimination) result, the compare signal detector outputs a signal tothe hit signal bus HBS at full amplitude, and precharges the match lineML, thereby completing the search operation and returning the cell tothe wait state.

Description will be made below of the search operation for the thirddata in a T-CAM. Though not shown in FIG. 6, the search operation fordata X or data MASK can be easily understood from the above descriptionof the search operation for binary data. When the entry is data X, thetransistors T4 and T6 are turned off since both storage nodes N1 and N2are held at a low voltage. Therefore, no current path is formed betweenthe match line ML and the grounded electrode whichever search key isentered, holding the match line ML at the precharge voltage VPCH. As aresult, the comparison indicates a hit.

When, on the other hand, the search key is data MASK, the mask signaldescribed above forces both search lines to be held at the groundpotential VSS. In this case, since the transistors T3 and T5 are off, nocurrent path is formed between the match line ML and the groundedelectrode whatever data the entry may be, holding the match line ML atthe precharge voltage VPCH. As a result, the comparison also indicates ahit.

FIG. 7 shows truth values for the above operations. Specifically, thesearch key and the entry each has three possible values, and theircombinations (9 combinations) and the corresponding comparison resultsindicate the 9 search operations carried out in a T-DCAM cell having theconfiguration shown in FIG. 1.

The above description of the search operations assumes that only asingle T-DCAM cell is connected to the match line. In an actual array,however, T-DCAM cells are arranged in a matrix, as shown in FIG. 4, anda plurality of cells are connected to each match line.

Therefore, in a search operation, a match line is held at the prechargevoltage VPCH only when all cells connected to it produce a hit. If anyone of the cells produces a miss, the match line is discharged, that is,the comparison result is a miss.

<<Description of Refresh Operation>>

Description will be made below of the refresh operation of a T-DCAM cellhaving the configuration shown in FIG. 1. The refresh operation will bedescribed with reference to FIG. 8 by focusing on cell CL11 in the arrayconfiguration shown in FIG. 4 in order to facilitate the understandingof the operation.

It should be noted that N1jk and N2jk (j=1, 2, m; k=1, 2, . . . , n)denote the storage nodes within the cells CLjk, while M1jk and M2jkdenotes the intermediate nodes within the cells CLjk. In FIG. 8 showingthe (voltage) waveforms of the storage nodes, the solid lines indicatewaveforms obtained when the cell CL11 stores data 1, while the brokenlines indicate waveforms obtained when the cell CL11 stores data 0. Therefresh operation of the present embodiment is characterized by thefollowing two arrangements. One is that that each search line isselectively activated to read out stored data for each column and outputit to the match line, and then a rewrite operation is carried out foreach column by use of the compare signal detector, the rewrite datalines, and the rewrite column select lines. The other arrangement issuch that the data stored at each storage node within the cell issequentially refreshed.

In the wait state, all match lines are precharged to the prechargevoltage VPCH, and the other signals (lines) are held at the groundpotential VSS. Then, if a column address generated by a refresh counter(described later) has been input to the search/bit line controller SBCTLthrough the data bus DBS, the search line SL21 set at the groundpotential VSS is driven to the power supply voltage VDD with the searchline SL11 held at the ground potential VSS, turning off the transistorT5 and turning on the transistor T3. As a result, conduction occursbetween the match line ML1 and the intermediate node M111. At that time,if the T-DCAM cell stores data 1, the transistor 4 is on since thestorage node N111 is at a high voltage. Therefore, a current path isformed between the match line ML1 and the grounded electrode, and thematch line ML1 is discharged from the precharge voltage VPCH toward theground potential VSS. If, on the other hand, the T-DCAM cell stores data0 or data X, the transistor 4 is off since the storage node N111 is at alow voltage. Therefore, no current path is formed between the match lineML1 and the grounded electrode, and the match line ML1 is held at theprecharge voltage VPCH.

As in the search operation described above, when the difference betweenthe precharge voltage VPCH and the voltage of the match line, which iscurrently being discharged, has become equal to (the voltage level of)the compare signal VSIG (corresponding to the read signal), the searchline SL2 set at the power supply voltage VDD is driven to the groundpotential VSS, thereby completing the reading of the stored data.

Then, the compare signal detector CSDTC discriminates the voltage of thematch line ML1 and outputs to the rewrite data line RWD1 a signal havinga voltage level corresponding to the discrimination result. Havingcompleted the discrimination of the compare signal, the compare signaldetector CSDTC can precharge the match line ML1 to the precharge voltageVPCH for the wait state, as shown in FIG. 8. Furthermore, since thecolumn address generated from the refresh counter has also been input tothe rewrite column select circuit, a rewrite line RW21 corresponding tothe search line SL21 is driven from the ground potential VSS to theboosted dc voltage VPP. Thus, the transistor T7 is turned on to rewriteto the storage node N111. Lastly, when the voltage of the storage nodeN111 has reached a voltage level substantially equal to that of therewrite data line RWD1, the rewrite line RW21 set at the boosted dcvoltage VPP is driven to the ground potential VSS and furthermore therewrite data line RWD1 is also driven to the ground potential VSS,thereby returning the cell to the wait state. It should be noted thateven though the above description focuses on the cell CL11, the storagenodes N1jl (j=2, 3, . . . , m) within the cells CLjl in the same columnas the CL11 are refreshed in the same manner through their correspondingmatch lines and rewrite data lines (at the same time).

The foregoing is a description of the portion of the refresh operationexecuted in a first single access. There are two method of refreshing(the other storage nodes in the same column and the storage nodes of)the remaining cells, as described below. One method is to first accessthe other storage nodes in the same column, and then access the storagenodes in the next column by incrementing the refresh counter.Specifically, first the search line SL21 is activated to refresh thestorage nodes N1j1 (j=1, 2, . . . , m) within the cells CLj1 (j=1, 2, .. . , m), as described above. Then, the search line SL11 is activatedaccording to an internal control signal (described later) to refresh thestorage nodes N2j1 (j =1, 2, . . . , m). After thus refreshing the cellsCLj1 in the first column, the refresh counter is incremented to refreshthe cells CLj2 (j=1, 2, . . . , m) in the second column. Theseoperations are repeated on the subsequent columns to refresh all cells.This type of refresh operation provides longer intervals betweentransitions in the column address signal, making it possible to reducethe power consumption of the refresh counter and the data bus DQS.

The other method is to increment the refresh counter each time access ismade so as to access a subsequent column. First of all, the search lineSL21 is activated to refresh the storage nodes N1j1 (j=1, 2, . . . , m)within the cells CLj1 (j =1, 2, . . . , m) in the first column, asdescribed above. After thus refreshing the storage nodes N1j1, therefresh counter is incremented and thereby the search line SL22 isactivated to refresh the storage nodes N1j2 (j=1, 2, . . . , m) withinthe cells CLj2 (j=1, 2, . . . , m) in the second column. Theseoperations are repeated on the subsequent columns to refresh the storagenodes N1jk (j=1, 2, . . . , m; k=1, 2, . . . , n) on one side. Then, thesearch lines SL1k (k=1, 2, . . . , n) are sequentially activatedaccording to the internal control signal to refresh the other storagenodes N2jk (j=1, 2, . . . , m; k=1, 2, . . . , n). At that time, therefresh counter is incremented each time access to a next column is tobe made.

It should be noted that the read operation on the cell shown in FIG. 1is similar to the above refresh operation, as described in detail later.Therefore, the read operation requires a counter for generating a columnaddress. The above refresh counter (for the first access method) may beused as this counter, making it possible to reduce the chip area.Further, if the refresh counter for implementing the second accessmethod is used as this counter, since the number of accesses requiredfor the second access method to read out all data within the array ishalf of that for the first access method, the time required for the readoperation can be reduced.

<<Description of Read Operation>>

With reference to FIG. 9, description will be made below of the readoperation of a T-DCAM cell having the configuration shown in FIG. 1. Theread operation of the present embodiment has the following threecharacteristics. First, as in the read operation for the refreshoperation, a search line is selected to read out stored data and outputit to the match line, and then the compare signal detector discriminatesthe read signal (corresponding to the comparison signal). Second, it isa nondestructive readout. The third characteristic is that access isrepeated on a column basis to read out the entry at a desired rowaddress one bit at a time. The following description of the operationassumes that in the array configuration shown in FIG. 4, the firstentries of the cells CL1k (k=1, 2, . . . , n) in the first row are to beread out, and focuses on the cell CL11.

In the wait state, all match lines are precharged to the prechargevoltage VPCH, and the other signals (lines) are held at the groundpotential VSS. Then, if a column address generated by a read counter(described later) has been input to the search/bit line controller SBCTLthrough the data bus DBS, the search line SL21 set at the ground voltageVSS is driven to the power supply voltage VDD, thereby driving the matchline ML1 to a voltage corresponding to the data stored in the cell CL11.

Then, as in the search and refresh operations described above, when thedifference between the precharge voltage VPCH and the voltage of thematch line ML1, which is currently being discharged, has become equal to(the voltage level of) the compare signal VSIG, the search line SL21 setat the power supply voltage VDD is driven to the ground potential VSS,completing the reading of the cells CLj1 (j=1, 2, . . . , m) in thefirst column. Subsequently, the compare signal detector CSDTCdiscriminates the voltage of the match line ML1 and outputs to the hitsignal bus HBS a signal having a voltage level corresponding to thediscrimination result. Lastly, the compare signal detector CSDTCprecharges the match line ML1 to the precharge voltage VPCH, therebyreturning the CAM array to the wait state.

It should be noted that here no rewrite operation is required for T-DCAMcells having the configuration shown in FIG. 1. The reason for this isthat the storage nodes of a cell are kept in a floating state while thecell is being accessed. This means that there exists nothing thataffects the stored charge except for small leakage currents of thetransistors T1, T2, T7, and T8. That is, the above operation is aso-called “nondestructive” read operation. It should be noted that eventhough the above description focuses on the cell CL 11, the data storedwithin the cells CLj1 (j=2, 3, . . . , m) in the same column as the CL11are also read out to their corresponding match lines in the same manner,and signals corresponding to the discrimination results are output tothe hit signal bus HBS. The data thus read out from the cells CLj1 (j=1,2, . . . , m) in the first column is transferred to a multiplexer(described later) through the hit signal bus HBS. Then, the data fromthe cell CL11 at the desired row address is selected and transferred tothe read register (described later).

This completes the read operation on the entry in the desired first-rowfirst-column cell. As is easily understood, the data of the cells in thesecond and subsequent columns is read out in the same manner. That is,in the read operation on the second column, the read counter isincremented to drive the search line SL22 set at the ground potentialVSS to the power supply voltage VDD and thereby read from the cells CLj2(j=1, 2, . . . , m) in the second column. That is, in the present readoperation, the data in each column is serially read out. It should benoted that as described in connection with the refresh operation, therefresh counter may be used as the read counter for generating a columnaddress, making it possible to reduce the chip area.

<<Overall T-CAM Configuration Example>>

Description will be made below of an overall configuration of a T-CAMemploying a T-CAM array having the above array configuration whichincludes T-DCAM cells having the above cell configuration (theoperations of a T-CAM array having such an array configuration andT-DCAM cells having such a cell configuration are also described above).FIG. 10 is a block diagram showing the main components of the T-CAM. TheT-CAM comprises a CAM array CAMARY, a data input/output circuit DIO,registers, a CAM controller CAMCTL, a flag logic circuit FLGC, a refreshcounter RFCNT, a read counter RDCNT, a priority encoder PENC, amultiplexer MUX, a demultiplexer DMX, and a static random access memory(SRAM) controller SRAMCTL. The CAM array CAMARY has the configurationshown in FIG. 4. The data input/output circuit DIO is disposed betweenmultiple external data DQ and a data bus DBS within the chip, andtransmits/receives data, address signals, and control signals forestablishing various settings of the chip.

The registers have a number of bits corresponding to the number ofsignal lines for their corresponding external data DQ. The figure showstwo registers for receiving data through the data bus DBS: a maskregister MKREG and a comparand register CPREG. The first mask registerMKREG stores data for generating the third data X or MASK for a desiredbit and inputs it to the CAM array CAMARY through a mask signal busMKBS. The comparand register CPREG stores the search key entered in asearch operation. This search key is written into the CAM array CAMARYwhen no entry coinciding with the search key has been found in thesearch operation.

The figure further shows three registers for receiving an address signalthrough the data bus DBS: a burst write register WREG, anext-free-address register NREG, and a burst read register RREG. Theburst write register WREG stores a row address and a burst length forthe first cycle in a burst write operation, and automatically counts upso as to generate addresses for the second and subsequent cycles afterthe burst write operation has begun. The next-free-address register NREGstores a row address at which no entry exists. The burst read registerRREG stores a row address and a burst length for the first cycle in aburst read operation, and automatically counts up so as to generateaddresses for the second and subsequent cycles after the burst readoperation has begun. The address signals generated by these registersare input to the CAM array CAMARY and the multiplexer MUX (describedlater) through the row address bus XBS.

The figure still further shows three registers for receiving controlsignals through the data bus DBS: an instruction register ISREG, aninformation register IFREG, and a configuration register CFREG. Theinstruction register ISREG stores control signals entered through thedata bus DBS and defines the chip initialization method, the number ofT-CAM chips connected in series, and the table configuration within thechip. It should be noted that the table configuration is a configurationof logical CAM arrays determined according to the number of entries andthe bit width of the entries. The information register IFREG stores aunique device number assigned to the chip in the system. Theconfiguration register CFREG stores, for example, a multiple matchsignal (described later) for controlling activation of the CAM arrayCAMARY logically divided as described above, and an enable signal forindicating whether or not each SRAM clock is valid.

In addition, FIG. 10 also shows a match address bus MABS, a matchaddress register MAREG inserted between a read data bus RDBS and thedata bus DBS, and a read data register RDREG.

The CAM controller CAMCTL generates a read acknowledge signal ACK, anend-of-transfer signal EOT, and internal command signals according to aninput external clock CLK and multiple external command signals CMD. Theexternal command signals CMD are generated from an external control chipusing an application specific integrated circuit (ASIC), etc. The readacknowledge signal ACK is a strobe signal output in synchronization withthe read data during a read operation, while the end-of-transfer signalEOT is a flag signal output in synchronization with the final data in aburst read operation.

It should be noted that the internal command signals are omitted fromthe figure for simplicity. In reality, however, a plurality of commandsignals are distributed to each circuit block according to theoperation. One of these command signals is output to the CAM arrayCAMARY to, for example, selectively activate the search lines and therewrite select lines, as described in connection with the refreshoperation.

A flag logic circuit FLGC is used to exchange full signals between T-CAMchips. For example, to achieve a high speed table search operation in arouter, a plurality of T-CAMs are generally connected in series so as tocreate a search table having a large capacity. Therefore, multiplefull-in signals FIN and multiple full-out signals FOUT are exchangedbetween chips to check the use conditions of each CAM array and controlto which CAM array a new entry is to be entered for storage. Inaddition, the flag logic circuit FLGC activates a multiple match signalMM when a plurality of entries have been hit in a search operation. Therefresh counter RFCNT generates a column address according to therefresh operation. This address is input to the CAM array CAMARY throughthe data bus DBS. The read counter RDCNT generates a column addressaccording to the read operation. This address is also input to the CAMarray CAMARY through the data bus DBS. It should be noted that asdescribed in connection with the refresh operation, a single counter maybe used as both the refresh counter and the read counter, making itpossible to reduce the chip area.

In a search operation, according to a signal entered from the hit signalbus HBS, the priority encoder PENC generates an address signalcorresponding to an entry which has been found to coincide with thesearch key. It should be noted that the priority encoder PENC has afunction to, if a plurality of entries have been hit, sequentiallyoutput address signals corresponding to them in the order of decreasingpriority (for example, the entry whose corresponding row address is thelowest has the highest priority). The generated address signals areinput to the match address register MAREG through the match address busMABS.

The multiplexer MUX receives signals from the hit signal bus HBS,selects one which corresponds to the row address stored in the aboveburst read register RREG, and outputs it to a read data line RD. Thedemultiplexer DMX transfers the data input from the read data line RD tothe signal line of the read data bus RDBS whose column numbercorresponds to the column address generated by the above read counterRDCNT.

According to a signal input from the data bus DBS, the SRAM controllerSRAMCTL outputs a signal for controlling SRAM(s) operating with thisT-CAM. FIG. 10 shows a SRAM clock SCLK, multiple SRAM control signalsSCTL, and a SRAM address SADD. The multiple SRAM control signals SCTLinclude, for example, a chip enable signal and a write enable signal.The SRAM address SADD is the address signal generated by the priorityencoder PENC as described above. When a plurality of address signalshave been generated, the SRAM controller SRAMCTL sequentially outputsaddresses entered through the data bus DBS from the match addressregister MAREG.

With this arrangement, a T-CAM employing T-DCAM cells having theconfiguration shown in FIG. 1 can perform various operations as follows.An entry can be input to the CAM array CAMARY through the data bus DBSby use of the burst write register WREG and the next-free-addressregister NREG. Further, a search key can be input to the CAM arrayCAMARY through the data bus DBS to perform a search operation. At thattime, if an entry coinciding with the search key is found, the priorityencoder PENC can generate an address signal corresponding to the entryand output it to an external SRAM through the match address registerMAREG and the SRAM controller SRAMCTL.

Still further, a column address generated by use of the refresh counterRFCNT can be input to the CAM array CAMARY through the data bus DBS toperform a refresh operation through the match lines and the rewrite datalines as described above. Still further, column and row addresses can begenerated by use of the read counter RDCNT and the burst read registerRREG, respectively, and thereby a desired entry in the CAM array CAMARYcan be read by use of the multiplexer MUX, the demultiplexer DMX, andthe read data register RDREG through serial-to-parallel conversion, asdescribed above.

<<T-DCAM Cell Structure Example>>

Description will be made below of a structure example of the T-DCAM cellshown in FIG. 1. FIGS. 11 to 14 show portions of the layout of a T-CAMarray. This structure is characterized in that all transistors areplanner transistors, and the internal nodes are connected to one anotherby use of a manufacturing technique called “shared contact”, which iswidely used for SRAMs. In these figures, each rectangle CAREA depictedby a thick broken line indicates the area of a single cell and thereforeshould not be confused with any layout pattern. Further, even though thefigures show only boundary portions of the neighboring cells, eachneighboring cell is disposed such that it is symmetrical to the targetcell about one of the four sides of the rectangle CAREA.

First of all, FIG. 11 will be described. The figure shows a first metallayer and the layers thereunder. Reference numeral FL denotes thepatterns of active areas; FP, the pattern of a first polysilicon layeron a silicon substrate for forming therein the gate electrodes oftransistors, word lines WL, etc.; FTM, the pattern of the first metallayer for forming a rewrite data line RWD, etc. therein; FCT, thepattern of a first contact for connecting an active area and the firstmetal layer; GCT, the pattern of a gate contact for connecting the firstpolysilicon layer and the first metal layer; and SHC, the pattern of ashared contact for connecting an active area and the first polysiliconlayer.

FIG. 12 will be described below. In the figure, the following twopatterns are added to the layout shown in FIG. 11. Reference numeral SMdenotes the pattern of a second metal layer for forming therein bitlines BL1 and BL2, rewrite column select lines RW1 and RW2, a groundpotential VSS supply line VG, etc. Reference numeral FTH denotes thepattern of a first throughhole for connecting the first metal layer andthe second metal layer.

FIG. 13 will be described below. In the figure, the following twopatterns are added to the layout shown in FIG. 12. Reference numeral TMdenotes the pattern of a third metal layer for forming a match line MLtherein, while STH denotes the pattern of a second throughhole forconnecting the second metal layer and the third metal layer.

Lastly, FIG. 14 will be described below. In the figure, the followingtwo patterns are added to the layout shown in FIG. 13. Reference numeralFRM denotes the pattern of a fourth metal layer for forming search linesSL1 and SL2 therein, while TTH denotes the pattern of a thirdthroughhole for connecting the third metal layer and the fourth metallayer. These patterns are formed by use of a known photolithographictechnique. It should be noted that the figures indicate each patternname with its corresponding node (or line) name in parentheses next toit. Therefore, it will be easily understood that the T-DCAM cell islocated at (or located in an area roughly defined by) the intersectionpoints between the word line WL and the pair of bit lines or searchlines and between the match line ML and the pair of bit lines or searchlines.

FIG. 15 is a schematic cross-sectional view of the structure shown inFIG. 14 taken along line A-A′. Reference numeral 100 denotes a p typesemiconductor substrate; 101, an insulator buried within the p typesemiconductor substrate for separating the device; 102, an n typediffusion layer region in the pattern of an active area FL shown in FIG.4; 103, the gate oxide film of a transistor formed on the substrate;104, the gate electrode of the transistor formed on the substrate; and105, a sidewall made up of an insulation film provided on the transistorformed on the substrate. Further, reference numeral 200 denotes thefirst metal layer used as the rewrite data line RWD, etc.; 201, thesecond metal layer used as the bit lines BL, the rewrite column selectlines RW, etc.; 202, the third metal layer used as the match line ML,etc.; and 203, the fourth metal layer used as the search lines SL. Stillfurther, reference numeral 300 denotes a first contact for connectingthe n type diffusion layer region 102 and the first metal layer; 301, afirst throughhole for connecting the first metal layer and the secondmetal layer; 302, a second throughhole for connecting the second metallayer and the third metal layer; and 400, an interlayer insulation film.This figure also indicates each layer name with its corresponding node(or line) name in parentheses next to it, as in FIGS. 11 to 14. Forexample, the arrangement of the transistors T3, T4, T5, and T6 forperforming XNOR operation can be easily understood from the node name ofeach gate electrode indicated by reference numeral 104 in FIG. 15.

The T-DCAM cell of the present embodiment employs shared contactpatterns as shown in FIG. 11, making it possible to reduce the arearequired for connecting the internal nodes. Assume that the followingfour rules are applied to the layouts shown in FIGS. 11 to 14. First,the minimum value for the wiring width and wiring interval of each layeris set to F (F: minimum feature size). Second, the patterns of eachcontact and each throughhole are square with a side dimension of F.Third, the optical alignment margins between the active areas and thefirst contacts and between the first polysilicon (layer) and the gatecontacts are set to (0. 5)*F. The fourth rule is such that the opticalalignment margins for connection between each contact and each metallayer and between each throughhole and each metal layer are set to zero.With these layout rules, ground potential VSS supply lines VG can bedisposed at a pitch of 19*F and word lines WL can be disposed at a pitchof (13.5)*F, making it possible to produce a T-DCAM cell having a cellarea of (256.5)*F².

The effects of the above T-DCAM cell configurations and operations aresummarized as follows.

First, the T-DCAM cell of the present embodiment is configured such thatthe rewrite data line RWD is provided in parallel with the match lineML, and the transistors T7 and T8 are inserted between the rewrite dataline RWD and the storage nodes N1 and N2, respectively, allowing storeddata to be read out to the match line ML and refreshed. Thus, the T-DCAMcell of the present embodiment is composed of only transistors. Whendata is read out from the memory cell, which has a small storage nodecapacity, a read signal is generated or not generated generallydepending on whether a current path is formed between a signal linehaving a sense amplifier connected thereto and the grounded electrodethrough a transistor channel in which the gate electrode forms a storagenode. In the configuration shown in FIG. 1, the search operation and therefresh operation are carried out by use of a common current path formedbetween the match line ML and the grounded electrode, making it possibleto perform refresh operation without reducing the XNOR operation speed.Thus, this arrangement allows providing a high-speed T-CAM arrayemploying T-DCAM cells made up of only transistors.

Second, the T-DCAM cell of the present embodiment performs a refreshoperation as described above in which the stored data is not read out tothe bit line BL, eliminating the need for providing a sense amplifierfor each bit line, which is required by a conventional T-CAM, making itpossible to reduce the array area as much. As a result, a highlyintegrated T-CAM array can be produced, resulting in a T-CAM having alarge capacity and a high cell occupancy ratio.

<Second Embodiment>

Description will be made below of another T-DCAM cell structure example.This structure is characterized in that vertical transistors are used asthe transistors T1, T2, T7, and T8 in the configuration shown in FIG. 1.The following description assumes that the vertical transistors are asdescribed in FIG. 1 of Japanese Laid-Open Patent Publication No.2000-269457. The structure will be described with reference to FIGS. 16,17, 18, 19, and 20. These figures show portions of the layout of a T-CAMarray. In the figures, each rectangle CAREA depicted by a thick brokenline indicates the area of a single cell and therefore should not beconfused with any layout pattern. Further, even though the figures showonly boundary portions of the neighboring cells, each neighboring cellis disposed such that it is symmetrical to the target cell about one ofthe four sides of the rectangle CAREA.

First of all, FIG. 16 will be described. The figure shows a second metallayer and the layers thereunder. Reference numeral FL denotes thepattern of an active area; FP, the pattern of a first polysilicon layeron a silicon substrate for forming therein the gate electrodes oftransistors, search lines SL, etc.; SP, the pattern of a secondpolysilicon layer for forming the drain electrodes of the verticaltransistors therein; FCT, the pattern of a first contact for connectingthe active area and a first metal layer; SCT, the pattern of a secondcontact for connecting the second polysilicon layer and the first metallayer (described later); and GH, the pattern of a gate hole for formingthe gate electrode of a vertical transistor.

FIG. 17 will be described below. The figure shows the first metal layerand the layers thereunder. The following four patterns are added to thelayout shown in FIG. 16. It should be noted that the second polysiliconlayer SP is omitted from FIG. 17, for simplicity. Reference numeral FTMdenotes the pattern of the first metal layer for forming a word line WL,etc. therein; FTH, the pattern of a first throughhole for connecting thefirst metal layer and a second metal layer (described later); TP, athird polysilicon layer formed as a buffer layer for connecting the gateelectrode of a vertical transistor and the first metal layer; and TCT,the pattern of a third contact for connecting the third polysiliconlayer and the first metal layer.

FIG. 18 will be described below. In the figure, the following twopatterns are added to the layout shown in FIG. 17. Reference numeral SMdenotes the pattern of the second metal layer for forming thereinrewrite column select lines RW, a ground potential VSS supply line VG,etc.; and STH denotes the pattern of a second throughhole for connectingthe second metal layer and a third metal layer.

FIG. 19 will be described below. In the figure, the following twopatterns are added to the layout shown in FIG. 18. Reference numeral TMdenotes the pattern of the third metal layer for forming therein a matchline ML, a rewrite data line WRD, etc.; and TTH denotes the pattern of athird throughhole for connecting the third metal layer and a fourthmetal layer (described later).

Lastly, FIG. 20 will be described. In the figure, the pattern of thefourth metal layer for forming bit lines BL therein is added to thelayout shown in FIG. 19. These patterns can be formed by use of a knownphotolithographic technique. It should be noted that the figuresindicate each pattern name with its corresponding node (or line) name inparentheses next to it. Therefore, it will be easily understood that theT-DCAM cell is located at (or located in an area roughly defined by) theintersection points between the word line WL and the bit lines BL1 andBL2 or search lines SL1 and SL2 and between the match line ML and thebit lines BL1 and BL2 or search lines SL1 and SL2.

FIG. 21 is a schematic cross-sectional view of the structure shown inFIG. 16 taken along line B-B′. Reference numeral 100 denotes a p typesemiconductor substrate; 101, an insulator buried within the p typesemiconductor substrate for separating the device; 103, the gate oxidefilms of transistors formed on the substrate; 104, the gate electrodesof the transistors formed on the substrate; and 105, a sidewall made upof an insulation film provided on a transistor formed on the substrate.Further, reference numeral 400 denotes an interlayer insulation film.Still further, reference numeral 500 denotes the gate electrode of avertical transistor; 501, the gate oxide film of the verticaltransistor; 502, a very thin polysilicon layer made of an intrinsicsemiconductor for forming therein a transistor channel and sourceelectrode; and 503, the second polysilicon layer for forming the drainelectrodes of vertical transistors.

FIG. 22 is a schematic cross-sectional view of the structure shown inFIG. 17 taken along line C-C′. Reference numeral 200 denotes the firstmetal layer (of this embodiment) formed as a buffer layer for connectingthe internal nodes. Further, reference numeral 301 denotes a firstthroughhole for connecting the first metal layer and the second metallayer. Still further, reference numeral 504 denotes the thirdpolysilicon layer for forming a buffer layer therein for connecting thegate electrodes of vertical transistors and the first metal layer; 505,a second contact for connecting the second polysilicon layer and thefirst metal layer; and 506, a third contact for connecting the thirdpolysilicon layer and the first metal layer. FIGS. 21 and 22 alsoindicate each layer name with its corresponding node (or line) name inparentheses next to it, as in FIGS. 16 and 17. For example, it will beeasily understood from the node name of each gate electrode indicated byreference numeral 104 that the vertical transistors in the figure arethe transistors T7 and T8 in the configuration shown in FIG. 1.Furthermore, it will also be easily understood that the current pathbetween the source and drain of each vertical transistor is formed in adirection perpendicular to the semiconductor substrate surface.

The T-DCAM cell of the present embodiment employs vertical transistorsas described above, thereby producing the following two effects. One isthat the cell area can be reduced. Assume, for example, that thefollowing four layout rules are applied to the layouts shown in FIGS. 16to 20. First, the minimum value for the wiring width and the wiringinterval of each layer is set to F (F: minimum feature size). Second,the patterns of each contact and each throughhole are square with a sidedimension of F. Third, the optical alignment margin between each contactand the electrode under it is set to (0.5)*F. The fourth rule is suchthat the optical alignment margin for connection between eachthroughhole and each metal wiring layer is set to zero. Use of thesefour rules allows the ground potential VSS supply lines VG and the wordlines WL to be disposed at pitches of 13*F and 9*F, respectively, makingit possible to produce a T-DCAM cell having a cell area of 117*F . Thisvalue is approximately one half of the cell area for the firstembodiment. Therefore, a highly integrated T-CAM having a large capacitycan be produced.

The other effect is that the retention characteristic is enhanced. Thechannels of the vertical transistors are formed of an intrinsicsemiconductor having a film thickness of only a few nanometers, asdescribed above, producing quantum confinement effect. Therefore, only avery small leakage current flows when the vertical transistors are off,making it possible to retain the charge at each node for a long periodof time. As a result, it is possible to reduce the power consumption ofthe T-CAM in the refresh operation.

<Third Embodiment>

Description will be made below of another T-DCAM cell configurationexample. FIG. 23 shows a cell configuration according to a thirdembodiment of the present invention. This configuration is characterizedin that capacitors C1 and C2 are added to the storage nodes N1 and N2,respectively, in the cell configuration shown in FIG. 1. When alltransistors are formed on the silicon substrate as described inconnection with the first embodiment, the capacitance values of thecapacitors C1 and C2 are set large enough that a desired retention timecan be obtained, considering (the stored data retention time and) theleakage currents of the transistors T1, T2, T7, and T8. Therefore, it ispossible to reduce the power consumption of the T-CAM in the refreshoperation. It should be noted that as is easily understood from theabove description, the capacitors C1 and C2 can also be added to thecell structure using vertical transistors described in connection withthe second embodiment. In this case, the retention characteristic can befurther enhanced.

<Fourth Embodiment>

Description will be made below of still another T-DCAM cellconfiguration example. FIG. 24 shows a cell configuration according to afourth embodiment of the present invention. This configuration ischaracterized in that the positions of the transistors T3 and T4 areswitched as well as those of the transistors T5 and T6. Specifically,the transistors T4 and T3 are connected between the match line ML andthe grounded electrode in that order, and the T6 and T5 are alsoconnected between these lines in that order. With this arrangement, inthe search operation and the read operation, the intermediate node M1 orM2 connected to the match line ML can be precharged to the same voltageas that of the match line ML. Therefore, in the search operation and theread operation, charge-sharing between the match line ML and theintermediate nodes M1 and M2 can be avoided, making it possible toproperly discriminate the compare signal generated on the match line ML.It should be noted that the above technique of the present invention canbe applied to the cell configuration shown in FIG. 23, producing thesame effect.

<Fifth Embodiment>

Description will be made below of still another T-DCAM cellconfiguration example. FIG. 25 shows a cell configuration according to afifth embodiment of the present invention. This configuration ischaracterized in that a single common line is used as both a bit lineand a search line. Specifically, the search line SL2 is connected to thedrain of the transistor T1 to act as the bit line BL1, while the searchline SL1 is connected to the drain of the transistor T2 to act as thebit line BL2. In this configuration, when data 1 or data 0 is entered,these search lines are driven to opposite polarities. For example, whendata 1 is entered in the write operation, the search line SL2 is drivento the power supply voltage VDD and the search line SL1 is driven to theground potential VSS. In the search operation, on the other hand, thesearch line SL2 is driven to the ground potential VSS and the searchline SL1 is driven to the power supply voltage VDD. It should be notedthat the match lines in the unselected rows are driven to the groundpotential VSS to prevent charging/discharging (thereof) in the writeoperation.

The above configuration and operation make it possible to reduce thenumber of lines and hence reduce the layout area. Furthermore, thenumber of wiring layers can be reduced, resulting a reduction in thenumber of masks to be employed, which leads to reduced cost per bit. Itshould be noted that the above technique of the present invention can beapplied to the cell configurations shown in FIGS. 23 and 24, producingthe same effect.

<Sixth Embodiment>

Lastly, description will be made below of still another T-DCAM cellconfiguration example. FIG. 26 shows a cell configuration according to asixth embodiment of the present invention. This configuration ischaracterized in that the transistors T4 and T6 in the cellconfiguration shown in FIG. 1 are connected to a discharge line DCL asshown in FIG. 2. This arrangement allows reducing the discharge current,thereby providing a T-CAM having reduced power consumption. It should benoted that the above technique of the present invention can be appliedto the cell configurations shown in FIGS. 23, 24, and 25, producing thesame effect.

The above descriptions explain T-DCAM cells having the rewritetransistors T7 and T8 therein. However, the present invention is notlimited to the configurations and operations described above, andvarious variations may be made thereto. For example, according to theabove embodiments, in the search operation and the refresh operation,the match line is precharged to a high voltage to generate the comparesignal VSIG.

However, the precharge voltage is not limited to high voltages. TheT-DCAM cells of the present invention can be applied to an operation inwhich the match line is precharged to the ground potential VSS asdescribed in Japanese Laid-Open Patent Publication No. 10-27481 (1998).In this case, the speed of the search operation can be furtherincreased.

Further, in the above descriptions, the present invention is describedas applied to off-chip T-CAM arrays. However, the present invention canbe applied to other types of CAMs (T-DCAM arrays). For example, thepresent invention may be applied to an on-chip T-CAM or a binary CAM forsearching for binary data. In either case, the same effect as that ofthe above embodiments can be obtained.

Thus, the present invention is applied to a T-CAM array having dynamicCAM cells and can provide a high-speed search operation and reducedarray area.

1. A semiconductor device, comprising: a match line extending in a firstdirection; a first search line and a second search line extending in asecond direction; a rewrite data line extending in said first direction;a comparison signal detecting circuit connected to said match line; anda plurality of memory cells each including a pair of first and seconddata retaining units, said first data retaining unit including a firsttransistor, a first storage node, and a first rewrite transistor, saidsecond data retaining unit including a second transistor, a secondstorage node, and a second rewrite transistor; wherein: said first andsecond storage nodes each hold written entry data; said first transistoris connected to said first storage node and transfers said data held bysaid first storage node to said match line according to signal voltagesof said search lines; said second transistor is connected to said secondstorage node and transfers said data held by said second storage node tosaid match line according to said signal voltages of said search lines;said first rewrite transistor is disposed between said first storagenode and said rewrite data line; and said second rewrite transistor isdisposed between said second storage node and said rewrite data line;wherein in a search operation, said semiconductor device performs stepsof: generating, on said match line, a signal corresponding to a resultof comparison between search key data entered from said search lines andsaid data held by said first and second data retaining units; anddiscriminating (detecting) said signal by use of said comparison signaldetecting circuit; and wherein in a refresh operation on said data heldby said first and second storage nodes, said semiconductor deviceperforms steps of: sequentially activating said first and second searchlines to generate, on said match line, a signal corresponding to saiddata held by said first and second data retaining units; discriminatingsaid signal by use of said comparison signal detecting circuit;transferring said discriminated data to said rewrite data line; andwriting said transferred data to said storage nodes through said rewritetransistors.